1. Field of Invention
The present invention relates to a fabrication method for a dynamic random access memory (DRAM). More particularly, the present invention relates to a method of fabricating a self-aligned ultra short channel.
2. Description of Related Art
As the size of the semiconductor device has gradually been reduced according to the design rule, a photolithographic process usually adopted in the semiconductor process reaches a bottleneck in terms of controlling the critical dimension, since the process is limited by light resolution and depth of focus. Such problem has a serious impact on area reduction of a memory cell.
Conventionally, a more complicated mask, such as a phase shift mask (PSM) and special exposure technology, such as off-axis illumination (OAI) are used to pattern a photoresist, so that the light resolution is improved. Although the critical dimension has been reduced as a consequence of the combination described above, the production cost of the integrated circuit has been greatly increased.
With advanced technology, the channel length of the MOS device is reduced during semiconductor process to significantly improve the operation speed of a transistor. However, problems such as short channel effects and associated hot electron effects occur when channel length is reduced to a certain extent, and consequently lead to an electrical breakdown. One solution to improve the short channel effects involves forming a doped region that has a lower doped concentration than that of a source/drain region, with the doped region known as a lightly doped drain (LDD) region.
In addition, the size of the memory cell and an area occupied by the DRAM capacitor have also been reduced, respectively, with respect to an increase in DRAM integration. Such size reduction for the memory cell can cause a decrease in a capacitance. In order to maintain the capacitance in an acceptable range, the high integration DRAM adopts a three-dimensional capacitor structure, such as a stacked capacitor, a trench stacked capacitor, and a crown shape capacitor to provide a large capacitor area. However, the increased complexity of the capacitor structure has caused an increase in the height of the capacitor and an increased capacitance in turns. Thus, a storage node consisting of a capacitor-over-bit line (COB) layout is developed, wherein the layout is not limited in terms of space for the capacitor.